teq is an architecture design and analysis toolkit
It's a replacement for simpleadl, whose goals were much more limited.
teq intends to support:
- the definition of a computer architecture, allowing both the basic architecture to be defined, and named extensions to be specified
- the creation of several different implementations of the architecture, these including:
- a simple uni-core functional simulator: a straightforward interpreted ISS
- a simple multicore functional simulator - a two-phase ISS
- a timing model, capable of having a set of parameterized core models execute correctly with correct timing for caches, MMU's, memory, interconnect and so forth.
- the creation of a simple assembler for the architecture
- a concurrent programming language and its compiler
- it would be nice to generate the compiler direct from the architecture and an implementation, but that's a step too far for the moment. Instead, the compiler generates triples, and the architect will need to specify the assembler code generated for each triple.
The status as of June 2020 is that
- architecture can be defined
- but - you can't define VLIWs
- ISS and assembler for uniprocessors are created and work
- the timing model is generatable and works
- the compiler understands a fair percentage of the language desired but doesn't yet handle structures, concurrency nor properly handling the calling of functions
The creation of the timing model allowed us to get back to basics in the creation of 'discrete event modeling' for processors. There's an article about this.